TSB12LV01A |
RFQ for TSB12LV01A Required Field |
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| Technical/Catalog Information | TSB12LV01AIPZ |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Controller Type | Link Layer Controller |
| Interface | IEEE 1394 |
| Voltage - Supply | 3 V ~ 3.6 V |
| Current - Supply | - |
| Package / Case | 100-LQFP |
| Packaging | - |
| Operating Temperature | -40°C ~ 85°C |
| Drawing Number | 296; 4040149; PZ; 100 |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | TSB12LV01AIPZ TSB12LV01AIPZ 296 11060 ND 29611060ND 296-11060 |
| Product | Manufacturers | Pack | D/C |
| TSB12LV01A | - | QFP100 | - |
The TSB12LV01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01A provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100Mbit/s, 200Mbit/s, and 400Mbit/s. The TSB12LV01A transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01A is capable of being cycle master and supports reception of isochronous data on two channels or all isochronous channels. TSB12LV01A has a generic 32-bit host bus interface, which connects to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user-configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).
The TSB12LV01A provides bus holding buffers on the PHY interface for simple and cost effective single-capacitor isolation. The TSB12LV01A is a revision of the TSB12C01A, with feature enhancements and corrections. All errata items t
Features |
| Link • Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus • Transmits and Receives Correctly Formatted 1394 Packets • Supports Isochronous Data Transfer• Performs Function of 1394 Cycle Master • Generates and Checks 32-Bit CRC • Detects Lost Cycle-Start Messages • Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K BytesPhysical-Link Interface • Interfaces Directly to the TSB11LV01, TSB14C01, TSB21LV03A, and TSB41LV0x PHY Chips • Supports Speeds of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s• Implements the Physical-Link Interface Described in Annex J of the IEEE 1394-1995 Standard • Supports TI Bus Holder Isolation External ImplementationHost Bus Interface• Provides Chip Control With Directly Addressable Registers• Is Interrupt Driven to Minimize Host Polling• Has a Generic 32-Bit Host Bus Interface General• Operates from a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs • Manufactured with Low-Power CMOS Technology• Packaged in a 100-Pin Thin Quad Flat Package (TQFP) (PZ Package) for 0°C to 70°C and 40°C to 85°C Operation |
